View ADP5065ACBZ-1-R7_3871832.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary technical data adp5065 rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? analog devices, inc. all rights reserved. fast charge battery manager with power path and usb compatibility features 3 mhz switch mode charger 1.25 a charge curr ent from dedicated charger up to 680 ma charging curr ent from 500ma usb host operating input voltage from 4.0v up to 5.5v tolerant input voltage -0.5v to 20v (usb vbus) dead battery isolation fet between battery and charger output battery thermistor input with automatic charger shutdown if battery temperature exceeds limits compliant with the jeita liion battery charging temperature specification sys_en_ok flag to hold off system turn-on until battery is at minimum required level for guaranteed system start-up due to minimum battery voltage and/or minimum battery charge level requirements eoc programming with c/20, c/ 10 and specific current level selection applications digital still cameras digital video cameras single cell li-ion portable equipment pdas, audio, gps devices mobile phones functional block diagram general description the adp5065 charger is fully compliant with the usb 2.0, usb 3.0 and usb battery charging specification 1.1 and enables charging via the mini-usb vbus pin from a wall charger, car charger, or usb host port. the adp5065 operates from a 4v to 5.5v input voltage range but is tolerant up to 20v. these alleviate the concerns of the usb bus spiking during disconnect or connect scenarios. the adp5065 also features an internal fet between the dcdc charger output and the battery. this permits battery isolation and hence system powering under a dead battery or no battery scenario which allows for i mmediate system function on connection to a usb power supply based on the type of usb source detected by an external the usb detection chip, the adp5065 can be set to apply the correct current limit for optimal charging and usb compliance. package and externals the adp5065 comes in a very small and low profile wlcsp-20 (0.5 mm pitch spacing) package. the overall solution requires only 5 small, low profile external components consisting of 4 ceramic capacitors (1 of which is the battery filter capacitor), 1 multi-layer inductor and 1 optional dead battery situation default setting resistor. this enables a very small pcb area to provide an integrated and performance enhancing solution to usb battery charging and power rail provision vin vbus ac or usb scl sda iin_ext trk_ext agnd + li-ion thr iso_b iso_s bat_sns adp5065 sys_on_ok v_weak_set system inductor 3mhz buck pgnd sw pgnd cfilt charger control block figure 1. adp5065 block diagram
adp5065 preliminary technical data rev. pra | page 2 of 22 table of contents features ............................................................................................... 1 ? applications ....................................................................................... 1 ? functional block diagram ........................................................... 1 ? general description .......................................................................... 1 ? package and externals ...................................................................... 1 ? table of contents ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 7 ? thermal resistance ....................................................................... 7 ? pin configurations and functional descriptions ........................ 8 ? typical performance characteristics .............................................. 9 ? temperature characteristics ...................................................... 10 ? typical waveforms ...................................................................... 12 ? theory of operation ....................................................................... 13 ? charger operational flowchart ................................................ 13 ? i 2 c register map ......................................................................... 14 ? register bit descriptions............................................................ 15 ? applications information ............................................................... 20 ? outline dimensions ........................................................................ 21 ? esd caution ................................................................................ 21 ? revision history revision pra: initial revision
preliminary technical data adp5065 rev. pra | page 3 of 22 specifications unless otherwise noted, -40 c < t j < 125 c, v vin = 5.0 v, v iso_s > 3.0 v, v hot < v thr < v cold , v bat_sns = 3.6 v, c vin = 2.2 f, c dcdc = 22 f, c bat = 22 f, c cfilt = 4.7 f l out = 1 h, all registers at default values parameter symbol min typ max unit test conditions / comments general parameters tolerable supply voltage v vin -0.5 20 v under-voltage lock-out v uvlo 2.3 2.4 2.5 v rising threshold, higher of v cfilt and v bat_sns 50 100 150 mv hysteresis, higher if v cfilt and v bat_sns falling total input current i vin 86 92 100 nominal usb initialized current level 1 150 usb super-speed 300 usb enumerated current level (chinese spec) 460 475 500 usb enumerated current level 900 dedicated charger input 1500 dedicated wall charger current consumption i qvin tbd current consumption i qiso_b 250 na sw pin leakage current -i out 2 a v vin = 0v charging parameters fast charge current, cc mode (battery voltage > v trk_dead ) i chg 1250 ma v cfilt > v bat_sns + v ccdrop 1, 2 fast charge current accuracy i chg(tol) -5 5 % t j = 25c, battery charging only operates between 0c and 115c (isothermal regulation) trickle charge current i trk_dead 20 ma 1, 2 weak charge current i chg_weak i chg + 20 ma when v trk_dead < v bat_sns < v weak but 1, 3 dead battery - trickle to weak charge threshold v trk_dead 2.5 v on bat_sns 1 trickle to weak charge threshold hysteresis v trk_dead 100 mv weak battery threshold C weak to fast charge threshold v weak 3.0 v on bat_sns, 1, 3 weak battery threshold hysteresis v weak 100 mv battery termination voltage v trm - 0.3% 4.200 + 0.3% v on bat_sns, t j = 25c, iend = 52.5ma 1 battery termination voltage v trm 4.158 4.200 4.242 v on bat_sns, t j = 0c to 115c 1 battery over voltage threshold v batov v cfilt C0.15 v relative to cfilt voltage, bat_sns rising charge complete current i end 52.5 ma v bat_sns = v trm 1 charging complete current threshold accuracy -30 30 % iend > 50ma recharge voltage differential v rch 260 mv relative to v trm, bat_sns falling 1 battery node short threshold voltage v bat_shr 2.4 v 1 charger dc-dc converter switching frequency f swchg 3 mhz maximum duty cycle d max 91 % peak inductor current i l(pk) 2000 ma regulated system voltage v iso_strk 3.244 3.3 3.366 v v bat_sns < v trk_dead, trickle charging mode load regulation 5 mv/a dc-dc power pmos on resistance r ds(on)p 220 m dc-dc power nmos on resistance r ds(on)n 150 m
adp5065 preliminary technical data rev. pra | page 4 of 22 parameter symbol min typ max unit test conditions / comments battery isolation fet bump to bump resistance between iso_b and iso_s bumps including bump resistances and battery isolation pmos on resistance r dsoniso 78 m on battery supplement mode, vin=0v v(iso_b)=3.6v, i(iso_b)=500ma regulated system voltage v iso_sfc 3.2 3.3 3.4 v v trk_dead < vbat_sns, fast charging cc mode maximum iso_b current i max_iso 1.5 2.2 a on battery supplement mode, vin=0v, v(iso_b)=3.6v, tj<85c battery supplementary threshold v thiso 0 5 10 mv v iso_s1:2 < v iso_b1:2 , vsys rising high voltage blocking fet vin input C high voltage blocking fet on resistance r dsonhv 350 m vin=5v, iin=500ma vin input current , suspend-mode i suspend 1.3 2.5 ma en_chg = low vin input voltage good threshold rising v vin_ok_rise 3.8 3.9 4.0 v vin input voltage good threshold falling v vin_ok_fall 3.6 3.67 v vin input over voltage threshold v vin_ov 5.35 5.42 5.5 v vin input over voltage threshold hysteresis 0.075 v cfilt total external capacitance 2.0 4.7 5.0 f vin transition timing - min rise time for vin from 5v to 20v t vin_rise 10 s vin transition timing - min fall time for vin from 4v to 0v t vin_fall 10 s thermal control isothermal charging temperature t lim 115 c thermal early warning temperature t sdl 130 c thermal shutdown temperature t sd 140 c t j rising thermal shutdown temperature t sd 110 c t j falling thermistor control thermistor current with 10k ntc i ntc_10k 400 a thermistor current with 100k ntc i ntc_100k 40 a thermistor capacitance c ntc 100 pf cold temperature limit i ntc_cold 0 c no battery charging occurs hot temperature limit i ntc_hot 60 c no battery charging occurs jeita specification 4 jeita cold temperature threshold i jeita_cold 0 c no battery charging occurs jeita cool temperature threshold i jeita_cool 10 c battery charging occurs at 50% of programmed level jeita typical temperature threshold i jeita_typ c normal battery charging occurs at default/programmed levels jeita warm temperature threshold i jeita_warm 45 c battery termination voltage (v trm ) is reduced by 100mv jeita hot temperature threshold i jeita_hot 60 c no battery charging occurs
preliminary technical data adp5065 rev. pra | page 5 of 22 parameter symbol min typ max unit test conditions / comments battery detection battery detection sink current i sink 20 ma battery detection source current i source 10 ma battery low threshold v batl 1.9 v battery high threshold v bath 3.4 v no battery threshold v nobat 3.3 3.0 v v trm 3.7v v trm < 3.7v battery detection timer t batok 333 ms timers start charging delay timer t start 1 s trickle charge timer t trk 60 min fast charge timer t chg 600 min charge complete timer t end 7.5 min v bat_sns = v trm , i chg < i end deglitch timer t dg 31 ms applies to v trk , v rch , i end , v dead, v vin_ok watchdog timer t wd 32 s 1 safety timer t safe 36 40 44 min battery node short timer t bat_shr 30 s 1 i 2 c compatible interface 5 capacitive load, each bus line c s 400 pf scl clock frequency f scl 400 khz scl high time t high 0.6 s scl low time t low 1.3 s data setup time t sudat 100 ns data hold time t hddat 0 0.9 s setup time for repeated start t susta 0.6 s hold time for start/repeated start t hdsta 0.6 s bus free time between a stop and a start condition t buf 1.3 s setup time for stop condition t susto 0.6 s rise time of scl/sda t r 20 300 ns fall time of scl/sda t f 20 300 ns pulse width of suppressed spike t sp 0 50 ns logic inputs maximum voltage on digital inputs v din_max 5.5 v maximum logic low input voltage v il 0.5 v applies to scl, sda, trk_ext, iin_ext minimum logic high input voltage v ih 1.2 v applies to scl, sda, source3:1, disable low level input current i il -1 1 a applies to scl, sda, source3:1, disable high level input current i ih tbd a applies to scl, sda, source3:1, disable high level input current tbd a applies to scl, sda pulldown resistance 350 k applies to source3:1, disable applies to trk_ext, iin_ext 1 these values are programmable via i 2 c. values are given with default register values. 2 the output current during charging may be limited by i bus , or by isothermal charging mode. 3 programmable via external resi stor programming if required. 4 jeita can be enabled or disabled in i 2 c. 5 a master device must provide a hold time of at least 300ns for the sda signal to bridge the un defined region of scls falling edge. the i 2 c timing diagram follows.
adp5065 preliminary technical data rev. pra | page 6 of 22 figure 2. i 2 c timing diagram.
preliminary technical data adp5065 rev. pra | page 7 of 22 absolute maximum ratings table 1. ad5065 absolute maximum ratings parameter rating vin1:2 to pgnd1:2 C0.5 v to +20v all other pins to agnd C0.3 v to +6 v ambient temperature range C40c to +85c storage temperature range C65c to +150c operating junction temperature range C40c to +125c soldering conditions jedec j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, i.e., ja is specified for device soldered in circuit board for surface mount packages. table 2. thermal resistance package type ja unit 5x4 array wlcsp 0.5mm pitch (2.75mm * 2.08mm) - based on a jedec, 2s2p, 4layer board with 0m/s airflow 55 c/w maximum power dissipation the maximum safe power dissipation in the adp5065 package is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150 c, which is the glass transition temperature, the plastic will change its properties. even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the adp5065. exceeding a junction temperature of 175 c for an extended period of time can result in changes in the silicon devices potentially causing failure.
adp5065 preliminary technical data rev. pra | page 8 of 22 pin configurations and functional descriptions figure 3. 20-ball wlcsp table 3. pin function descriptions 20-ball wlcsp name type description sw1:2 i/o dc-dc converter inductor connections C high current output in charging mode vin1:2 i/o power connections to usb vbus C high current input in charging mode pgnd1:2 g charger power ground pins C high current input in charging mode agnd g analog ground cfilt i/o 4.7uf filter capacitor connection C high current i/o in charging mode iso_s1:2 i/o charger supply side input to internal isolation fet / battery current regulation fet iso_b1:2 i/o battery supply side input to internal isolation fet / battery current regulation fet scl i i 2 c compatible interface serial clock sda i/o i 2 c compatible interface serial data iin_ext i sets the input current limit directly trk_ext i enables the trickle charge function thr i battery pack thermistor connection bat_sns i battery voltage sense pin sys_on_ok o battery ok flag output pin to enab le system once battery has reached v_weak v_weak_set i/o external resi stor setting pin for v_weak threshold (optional use) thr 4 3 2 1 e d c b a iin_ext scl v_weak_ set iso_b1 iso_b2 trk_ext sda iso_s1 iso_s2 sw1 pgnd1 vin1 sw2 pgnd2 sys_on_ ok cfilt vin2 corner top view bat_sns agnd
preliminary technical data adp5065 rev. pra | page 9 of 22 typical performance characteristics figure 4. battery charger efficiency vs. battery voltage, vin = 5.0 v figure 5. system voltage efficiency vs. output current, vin = 5.0 v figure 6. system voltage regulation vs. output current, vin = 5.0 v figure 7. usb limited battery charge current vs. battery voltage, vin = 5.0 v, ilim = 100 ma figure 8. usb compliant charge current vs. battery voltage, vin = 5.0 v, ilim = 500 ma figure 9. battery isolation fet resistance vs. battery voltage, vin = 5.0 v, load current = 1.0 a 0 10 20 30 40 50 60 70 80 90 100 2,50 2,90 3,30 3,70 4,10 4,50 efficiency [%] battery voltage [v] v in input limit 100 ma v in input limit 500 ma 0 10 20 30 40 50 60 70 80 90 100 0,01 0,10 1,00 efficiency [%] system output current [a] 3,25 3,26 3,27 3,28 3,29 3,30 3,31 3,32 3,33 3,34 3,35 0,001 0,010 0,100 1,000 system voltage [v] system output current [a] 0 20 40 60 80 100 120 140 2,70 3,00 3,30 3,60 3,90 4,20 battery charge current [a] battery voltage [v] 0 100 200 300 400 500 600 700 2,70 3,00 3,30 3,60 3,90 4,20 battery charge current [a] battery voltage [v] 70 75 80 85 90 95 100 2,70 3,00 3,30 3,60 3,90 4,20 ron resistance [m ? ] battery voltage [v]
adp5065 preliminary technical data rev. pra | page 10 of 22 temperature characteristics figure 10. vin over voltage protection rising threshold vs. ambient temperature. figure 11. system voltage vs. ambient temperature, vin = 5.0 v, r load = 33 figure 12. input current limit vs. ambient temperature, vin = 5.0 v figure 13. termination voltage vs. ambient temperature. vin = 5.0v figure 14. fast charge current vs. ambient temperature, vin = 5.0 v, viso_b = 3.6 v, ichg = 1050 ma figure 15. battery leakage current vs. ambient temperature 5,25 5,30 5,35 5,40 5,45 5,50 5,55 5,60 5,65 5,70 5,75 -40 -20 0 20 40 60 80 100 120 vin over voltage protection [v] ambient temperature [oc] 3,27 3,28 3,28 3,29 3,29 3,30 3,30 3,31 3,31 -40 -20 0 20 40 60 80 100 120 system voltage [v] ambient temperature [oc] 0 50 100 150 200 250 300 350 400 450 500 -40 -20 0 20 40 60 80 100 120 input current limit [ma] ambient temperature [oc] v in input limit 100 ma v in input limit 500 ma -1,0 % -0,5 % 0,0 % 0,5 % 1,0 % -40 -20 0 20 40 60 80 100 120 vtrm accuracy [%] ambient temperature [oc] vtrm = 3.50 v vtrm = 3.80 v vtrm = 4.20 v vtrm = 4.42 v 1,00 1,01 1,02 1,03 1,04 1,05 1,06 1,07 1,08 1,09 1,10 -40-20 0 20406080100120 charge current [a] ambient temperature [oc] 0,00 0,10 0,20 0,30 0,40 0,50 0,60 0,70 0,80 0,90 1,00 -40-20 0 20406080 battery leakage current [a] ambient temperature [oc] v(iso_b) = 2.7 v v(iso_b) = 3.6 v v(iso_b) = 4.2 v
preliminary technical data adp5065 rev. pra | page 11 of 22 figure 16. switching frequency vs. ambient temperature, vin = 5.0 v figure 17. vin quiescent current vs. temperature, vin = 5.0 v, suspend-mode (en_chg = 0) 2,90 2,92 2,94 2,96 2,98 3,00 3,02 3,04 3,06 3,08 3,10 -40 -20 0 20 40 60 80 100 120 switching frequency [mhz] ambient temperature [oc] 1,16 1,18 1,20 1,22 1,24 1,26 1,28 1,30 1,32 1,34 -40-20 0 20406080 input current [ma] ambient temperature [oc]
ad p typ i p 5065 i cal wave f figure 19 . figure 2 0 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,00 vin current [ma] v(iso_s) sw i sw v(iso_s) sw i sw f orms figure 18. vin cu r suspend-mo d . typical wavefor m 0 . typical wavefor m 2,00 3,0 0 v in v r rent vs. vin volta g d e (en_chg = 0) m s, vin = 5.0 v, i iso_ s m s, vin = 5.0 v, i iso _ 0 4,00 5 v oltage [v] rev. pr a g e, s = 1000 ma _ s = 100 ma 5 ,00 6,00 a | page 12 of 22 f i p figure 21 i gure 22. system v o 3,0 3,2 3,4 3,6 3,8 4,0 4,2 4,4 0 battery voltage [v] v(iso_s) i(iso_s) p relimina r 1 . charge profile, v i battery capacit y o ltage load transi e 1.0 a C 50 1 charge ti m v(bat_sns) i(iso_b) i(vin) 1 a r y techni c i n = 5.0 v, ilim = 5 y = 1320 mah e nt, vin = 5.0 v, l o C 0 a 1 00 150 m e [min] a c al data 00 ma, o ad transient 0 a C 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 current [a] 0 a
preliminary technical data adp5065 rev. pra | page 13 of 22 theory of operation charger operational flowchart figure 23. adp5065 operational flowchart
adp5065 preliminary technical data rev. pra | page 14 of 22 i 2 c register map table 4. i 2 c register map register d7 d6 d5 d4 d3 d2 d1 d0 0x00 manufacturer and model id manuf model 0x01 silicon revision rev 0x02 vin settings rfu ilim 0x03 termination settings vtrm iend 0x04 charging current c/20 eoc c/10 eoc high (read only) ichg itrk_dead 0x05 voltage threshold vrch vtrk_dead vweak 0x06 timer settings en_ tend en_ chg_ timer chg_ tmr_ period en_ wd wd period reset_ wd 0x07 functional settings1 en_jeita dis_ipk_s d en_ bmon en_thr x en_eoc en_trk en_chg 0x08 functional settings2 0x09 interrupt enable en_ind_p eak_ int en_ therm_ lim_int en_ wd_int en_ tsd_int en_ thr_int en_ bat_int en_ chg_int en_ vin_int 0x0a interrupt active ind_peak _int therm_ lim_int wd_int tsd_int thr_int bat_int chg_int vin_int 0x0b charger status 1 vin_ov vin_ok vin_ ilim therm_ lim chdone charger_status 0x0c charger status 2 thr_status ipk_stat battery_status 0x0d fault register bat_shr ind_peak _int tsdl 130?c tsd 140?c 0x10 battery short tbat_shr vbat_shr
preliminary technical data adp5065 rev. pra | page 15 of 22 register bit descriptions table 5. register bit descriptions bit(s) name access default description 0x00 manufacturer and model id register 7:4 manuf<3:0> r tbd 4-bit manufacturer identification bus 3:0 model<3:0> r tbd 4-bit model identification bus 0x01 silicon revision register 7:4 not used r 3:0 rev<3:0> r tbd 4-bit silicon revision identification bus 0x02 vin settings register 7:5 not used r 4 rfu r/w 0 reserved for future use 3:0 ilim<3:0> r/w 0000=100ma vin input current limit programming bus. the current into vin can be limited to the programmed values below 0000=100ma 1000=800ma 0001=150ma 1001=900ma 0010=200ma 1010=1000ma 0011=300ma 1011=1100ma 0100=400ma 1100=1200ma 0101=500ma 1101=1300ma 0110=600ma 1110=1400ma 0111=700ma 1111=1500ma 0x03 termination settings register 7:2 vtrm<5:0> r/w 100011=4.20v termination voltage programming bus. th e values of the float voltage can be programmed as per the values below 000000=3.50v 010000=3.82v 100000=4.14v 000001=3.52v 010001=3.84v 100001=4.16v 000010=3.54v 010010=3.86v 100010=4.18v 000011=3.56v 010011=3.88v 100011=4.20v 000100=3.58v 010100=3.90v 100100=4.22v 000101=3.60v 010101=3.92v 100101=4.24v 000110=3.62v 010110=3.94v 100110=4.26v 000111=3.64v 010111=3.96v 100111=4.28v 001000=3.66v 011000=3.98v 101000=4.30v 001001=3.68v 011001=4.00v 101001=4.32v 001010=3.70v 011010=4.02v 101010=4.34v 001011=3.72v 011011=4.04v 101011=4.36v 001100=3.74v 011100=4.06v 101100=4.38v 001101=3.76v 011101=4.08v 101101=4.40v 001110=3.78v 011110=4.10v 101110 to 001111=3.80v 011111=4.12v 111111=4.42v 1:0 iend<1:0> r/w 01=52.5ma termination current programming bus. the values of the termination current can be programmed as per the values below 00=32.5ma 10=72.5ma 01=52.5ma 11=92.5ma
adp5065 preliminary technical data rev. pra | page 16 of 22 bit(s) name access default description 0x04 charging current settings register 7 c/20 eoc r/w the c/20 bit has priority over the other settings (c/10 eoc and iend) when bit is high c/20 programming used. 27.5ma minimum value 6 c/10 eoc r/w the c/10 bit has priority over the other setting (end) but not c/20 eoc when bit is high c/10 programming us ed unless c/20 eoc is high. 27.5ma minimum value 5 tied high in metal r 1 4:2 ichg<2:0> r/w 111=1250ma fast charge current programming bus. the values of the constant current charge can be programmed as per the values below 000=550ma 001=650ma 010=750ma 011=850ma 100=950ma 101=1050ma 110=1150ma 111=1250ma 1:0 itrk_dead<1:0> r/w 10=20ma trickle and weak charge current pr ogramming bus. the values of the trickle nad weak charge currents can be programmed as per the values below 00=5ma 10=20ma 01=10ma 11=20ma 0x05 voltage threshold settings register1 7 not used r 6:5 vrch<1:0> r/w 11=260mv recharge voltage programming bus. th e values of the recharge threshold can be programmed as per the values below 00=80mv 10=200mv 01=140mv 11=260mv 4:3 vtrk_dead<1:0> r/w 01=2.5v trickle to fast charge dead battery vo ltage programming bus. the values of the trickle to fast charge threshold can be programmed as per the values below 00=2.4v 10=2.6v 01=2.5v 11=3.3v 2:0 vweak<1:0> r/w 011=3.0v weak battery voltage rising threshold. sets when the system is enabled by v_weak_ok signal: 000=2.7v 001=2.8v 010=2.9v 011=3.0v 100=3.1v 101=3.2v 110=3.3v 111=3.4v 0x06 timer settings register 7 not used 6 notused 5 en_tend r/w 1 when low disables the charge complete timer t end. a 31ms deglitch timer will remain on this function. 4 en_chg_ timer r/w 1 when high the trickle / fast charge timer is enabled 3 chg_tmr_ period r/w 1 trickle / fast charge timer period 0=30/300min 1=60/600min 2 en_wd r/w 1 when high the watchdog timer safety timer is enabled. when low the watchdog timer is disabled even if bat_sns exceeds v dead
preliminary technical data adp5065 rev. pra | page 17 of 22 bit(s) name access default description 1 wd period r/w 0 watchdog safety timer period 0=32sec/40min 1=64sec/40min 0 reset_wd w 0 high resets the watchdog sa fety timer. bit is reset automatically. 0x07 functional settings1 register 7 en_jeita r/w 0 when low, disables the jeita liion temperature battery charging specification 6 dis_ipk_sd r/w 1 when high this disabled the automatic shutdown of the device if 4 peak inductor current limits are reached in succession ? when high it will only flag a status bit ipk_stat 5 en_bmon r/w 0 when high battery monitor is enabled even if vin is below v vin_ok 4 en_thr r/w 0 when high thr current source is enabled even if vin is below v vin_ok 3 x r/w 2 en_eoc r/w 1 when high end of charge is allowed 1 en_trk r/w 1 when low trickle charger is disabled, dc-dc converter is enabled 0 en_chg r/w 1 when low dc-dc converter is disabled 0x08 functionl settings2 register 7:0 not used r/w 0x09 interrupt enable register 7 en_ind_peak_int r/w 0 when high inductor peak current limit interrupt is allowed 6 en_therm_ lim_int r/w 0 when high isothermal ch arging interrupt is allowed 5 en_wd_int r/w 0 when high watc hdog alarm interrupt is allowed 4 en_tsd_int r/w 0 when high over temperature interrupt is allowed 3 en_thr_int r/w 0 when high thr temper ature thresholds interrupt is allowed 2 en_bat_int r/w 0 when high battery vo ltage thresholds inte rrupt is allowed 1 en_chg_int r/w 0 when high charger mode change interrupt is allowed 0 en_vin_int r/w 0 when high vin volt age thresholds inte rrupt is allowed 0x0a interrupt active register, i 2 c read reset the register bits 7 ind_peak_int r 0 when high interrup t due to inductor peak current limit 6 therm_ lim_int r 0 when high interrupt due to isothermal charging 5 wd_int r 0 when high interrupt due to watchdog alarm. watchdog timer expires within 2sec / 4sec. 4 tsd_int r 0 when high interrupt due to over temperature fault 3 thr_int r 0 when high interrupt due to thr temperature thresholds 2 bat_int r 0 when high interrupt due to battery voltage thresholds
adp5065 preliminary technical data rev. pra | page 18 of 22 bit(s) name access default description 1 chg_int r 0 when high interrup t due to charger mode change 0 vin_int r 0 when high interrupt due to vin voltage thresholds 0x0b charger status register 1 7 vin_ov r n/a when high indicates that vin exceeds v vin_ov 6 vin_ok r n/a when high indicates that vin exceeds v vin_ok 5 vin_ilim r n/a when high indicates that the current into vin pin is limited by the high voltage blocking fet and the charger is not running at the full programmed i chg . 4 therm_lim r n/a when high indicates that the charger is not running at the full programmed i chg , but is limited by the die temperature. 3 chdone r n/a when high indicates the end of charge cycle has been reached. this bit will latch on, in that it will not reset to low when the v rch threshold is breached. 2:0 chager_ status<2:0> r n/a charger status bus. 000=off 100=charge complete 001=trickle charge 101=suspend 010=fast charge (cc-mode) 110=trickle or fast charge timer expired 011=fast charge (cv-mode) 111=battery detection 0x0c charger status register 2 7:5 thr_ status<2:0> r n/a thr-pin status 000=off 001=batcold 010=batcool 011=batwarm 100=bathot 111=thermistor ok 4 ipk_stat r n/a peak current limit status bit set high if 4 or more peak inductor current limits are reached in succession 3 not used r n/a 2:0 battery_ status<2:0> r battery status bus. 000=battery monitor off 001=no battery 010=bat_sns < v trk 011=v trk bat_sns < v weak 100=bat_sns v weak 0x0d fault register, i 2 c read + i 2 c write to reset the register bits 7:4 not used 3 bat_shr r/w 0 when high battery short detection has occured 2 ind_peak_int r/w 0 when high inductor peak current limit fault has occurred 1 tsd 130?c r/w 0 when high the over temperature (lower) fault has occurred 0 tsd 140?c r/w 0 when high the ov er temperature fault has occurred
preliminary technical data adp5065 rev. pra | page 19 of 22 bit(s) name access default description 0x10 battery short register 7:5 tbat_shr<2:0> r/w 100 = 30seconds battery short time-out timer: 000= 1s 001= 2s 010= 4s 011= 10s 100= 30s 101= 60s 110= 120s 111= 180s 4:3 not used r/w 2:0 vbat_shr<2:0> r/w 100=2.4v battery short voltage threshold level: 000= 2.0v 001= 2.1v 010= 2.2v 011= 2.3v 100= 2.4v 101= 2.5v 110=2.6v 111= 2.7v
adp5065 preliminary technical data rev. pra | page 20 of 22 applications information figure 24. adp5065 reference circuit diagram. figure 16. adp5065 pcb layout suggestion.
preliminary technical data adp5065 rev. pra | page 21 of 22 outline dimensions figure 25. 20 ball wlcsp package. dimensions shown in millimeters esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. table 6. ordering guide adp5065 products temperature package package description package outline ADP5065ACBZ-1-R7 C40c to +85c 20 ball wlcsp (0.5mm pitch) wlcsp
adp5065 preliminary technical data rev. pra | page 22 of 22 notes ? 2011 analog devices, inc. all rights reserved. trademarks and registered trad emarks are the proper ty of their respective companies. printed in the u.s.a. pr09370-0-8/11(pra)

▲Up To Search▲

Price & Availability of ADP5065ACBZ-1-R7

	To Download ADP5065ACBZ-1-R7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .